1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a bit line sensing circuit and method of a semiconductor memory device.
2. Description of Related Art
As semiconductor memory devices tend toward high integration and large capacity, higher speed operations are demanded. Typically, a dynamic random access memory (DRAM) consists of one access transistor and one storage capacitor, and data is stored in the storage capacitor. The data stored in the storage capacitor is transferred to a bit line through the channel of the access transistor, and the transferred data is amplified through a sense amplifier (sense amp) connected to the bit line and generated to the exterior.
In a semiconductor memory device which is capable of successively accessing data, after a data access operation, an operation for equalizing and precharging the bit line is implemented prior to the next access operation. Since the data access operation is executed to or from a memory cell, a pair of bit lines BL and BL are developed to a predetermined level for the next access operation. Therefore, as is well known, the bit lines BL and BL should be precharged to a prescribed level after being equalized. Similarly, a pair of PMOS and NMOS sense amps, which are connected between the bit line and a data input/output line and sense and amplify data, should be equalized and precharged to the same level.
For the high speed operation of the semiconductor memory device, it is very important to reduce the time required for data transferred to the bit line to be amplified through the sense amp. However, high integration is accompanied by low operating power voltage, which delay the operation speed of each circuit within the semiconductor memory device. Hence, it is difficult to reduce the bit line sensing time.
FIG. 1 illustrates a conventional bit line sensing circuit. A PMOS sense amp 40 and an NMOS sense amp 35 are respectively connected between bit lines BL and BL. The PMOS sense amp 40 includes a first PMOS transistor T3 having a source electrode connected to a sensing node LA, a drain electrode connected to the bit line BL and a gate electrode connected to the bit line BL, and a second PMOS transistor T4 having a source electrode connected to the sensing node LA, a drain electrode connected to the bit line BL and a gate electrode connected to the bit line BL. The NMOS sense amp 35 includes a first NMOS transistor T1 with a drain electrode connected to a sensing node LA, a source electrode connected to the bit line BL and a gate electrode connected to the bit line BL, and a second NMOS transistor T2 with a drain electrode connected to the sensing node LA, a source electrode connected to the bit line BL and a gate electrode connected to the bit line BL.
A third PMOS transistor 25 for supplying a power voltage VCC is connected to the sensing node LA. A third NMOS transistor 30 for supplying a ground voltage VSS is connected to the sensing node LA. First and second control signals LAPG and LANG are connected to gate electrodes of the third PMOS transistor 25 and the third NMOS transistor 30. If the third PMOS transistor 25 and the third NMOS transistor 30 are turned on, the power voltage VCC and the ground voltage VSS are supplied to the sensing nodes LA and LA respectively, thereby operating the PMOS sense amp 40 and the NMOS sense amp 35.
FIG. 2A shows a peak value of leakage current Iss versus the power voltage when a sensing window (an interval between starting the sensing operation of the PMOS sense amp 40 after starting the sensing operation of the NMOS sense amp 35) is 3 nanoseconds (ns) and 0ns. FIG. 2B shows sensing delay time versus the power voltage for the sensing windows of 3 ns and 0 ns.
In operation, after the data of the memory cell is conveyed to the bit lines BL and BL, the NMOS sense amp 35 carries out the sensing operation and the PMOS sense amp 40 performs a restore operation. However, if the bit lines BL and BL are precharged to half the power voltage VCC, that is, to (1/2)VCC, since a difference between gate-source voltages Vgs of the transistors T1 and T2 constituting the NMOS sense amp 35 becomes only a charge sharing voltage .DELTA.V, current flows into both transistors T1 and T2 the moment the sensing operation is started. Similarly, since the difference between the gate-source voltages Vgs of the transistors T3 and T4 constituting the PMOS sense amp 40 becomes only the charge sharing voltage .DELTA.V, current flows into both transistors T3 and T4.
When the NMOS sense amp 35 and the PMOS sense amp 40 simultaneously operate, the operation has nothing to do with the bit line sensing operation and a current path is formed. Thus the leakage current Iss increases. As is well known, since this bit line sensing operation is performed almost on the same time on all the bit lines, the peak value of the leakage current Iss greatly increases, ground voltage noise occurs and operating dissipation current increases.
To overcome these shortcomings, a PMOS sense amp enable signal PSE and an NMOS sense amp enable signal NSE are applied to a PMOS sense amp delay circuit 5 and an NMOS sense amp delay circuit 15 respectively, to generate respective first and second delay signals PISD and PSD. The delay signals PISD and PSD are supplied to first and second control signal generating circuits 10 and 20, to generate the first and second control signals LAPG and LANG for controlling the NMOS and PMOS sense amps 35 and 40, respectively. The bit line sensing circuit shown in FIG. 1 generates the second control signal LANG, and after a prescribed time generates the first control signal LAPG.
In the bit line sensing circuit shown in FIG. 1, the first and second delay signals PISD and PSD respectively supplied to the first and second control signal generating circuits 10 and 20 which respectively generate the first and second control signals LAPG and LANG for generating the PMOS and NMOS sense amps 40 and 35, are generated through respective delay paths. Therefore, the time to operate the NMOS and PMOS sense amps 35 and 40 can be controlled by controlling a delay time difference.
When the sensing window is 3 ns and 0 ns, that is, when the operating time of the NMOS sense amp 35 is before that of the PMOS sense amp 40, and when the former is the same as the latter, respectively, the peak value of the leakage current and the sensing delay time versus the power voltage VCC of 1.6-3.3 V are shown in FIGS. 2A and 2B. The obtained charts are from a 256K block model using cell capacitance of 30 pF and bit line capacitance of 240 pF. The sensing delay time is defined from the operating time of the NMOS sense amp 35 to the time a voltage difference between the bit lines BL and BL is VCC.times.0.3, and the peak value of the leakage current is obtained by measuring the maximum leakage current. As indicated, the sensing delay time increases and the peak value of the leakage current decreases with a decrease in the power voltage. At the same power voltage, the sensing window of 0 ns has large leakage current and short sensing delay time relative to the sensing window of 3 ns.
Therefore, the sensing current is generated irrespective of the bit line sensing operation, and is cut off by providing the sensing window, i.e., an interval between the operating times of the NMOS and PMOS sense amps. However, since the operating time of the PMOS sense amp is delayed by the sensing window interval, the entire sensing operating time increases.
On the other hand, in a semiconductor memory device used for battery back-up, since the power voltage is lowered according to the discharge of the battery, the operating speed is rapidly lowered and the leakage current is also sharply reduced. Therefore, in a memory device which is operated by a battery, for example, it is necessary to improve the operating speed even when the leakage current, which does not give rise to trouble at a low power voltage, increases.